The present invention generally relates to integrated circuits (IC), and more particularly to logic and memory ICs that utilize a multi-stage doping methodology to electrically adjust characteristics of a metal-oxide-semiconductor field effect transistor (MOSFET) and for reducing the size of the same.
As MOSFETs continuously downscale, the thermal budget, source/drain junction depth and dopant concentration are reduced for alleviating short channel effects. However, there is a limit to this trend of reduction. If the limit is exceeded, the lower poly gate doping profile can change, which may induce an undesirable depletion region between the gate electrode and the gate dielectric layer. If the gate dopant concentration does not saturate enough, it will increase the electrical gate dielectric thickness and degrade the MOSFET saturation current. The electrical gate dielectric thickness is the equivalent thickness of the gate dielectric layer under certain electrical conditions. Two MOSFETs with the same physical gate dielectric thickness may have different electrical gate dielectric thickness. For example, those two MOSFETs operating under different electrical conditions, e.g., with different gate dopant concentrations, can have significantly unmatched electrical gate dielectric thickness. In general, one of the MOSFETs may have a “thinner” electrical gate dielectric thickness than the other if it has a greater gate dopant concentration. As such, an insufficiently doped gate electrode usually results in an undesirably thick electrical gate dielectric thickness.
Conventionally, only a single-stage doping is performed for the gate structures of logic devices and memory cells in fabrication of an IC, such as SRAM and DRAM. For example, in an SRAM cell design, a pass gate device usually requires a narrower channel width and a longer channel length than a pull-down device, in order to obtain a high β ratio and static noise margin (SNM). However, such design will cause an inverse narrow width effect and decrease the β ratio in a low voltage operation. The long channel length design particularly causes the size of the memory cell to increase. An optimal design for an SRAM circuit should have a pass gate device with a higher threshold voltage and lower saturation current when compared to a pull-down device. As such, the electrical characteristics of the pass gate device and the pull-down device should be different.
A DRAM cell often includes a pass gate device coupled with a capacitor. In a DRAM cell design, the pass gate device leakage and capacitor gate leakage are the ones of major concerns. A lower gate leakage and sub-threshold leakage are desirable for a better data retention, reliability, and standby leakage current specification. In order to achieve these objectives, a thicker gate dielectric layer is needed for the pass gate device than other peripheral logic devices. This disparate thickness of gate dielectric layers complicates the fabrication process.
Desirable in the art of logic and memory devices fabrication are new MOSFETs with electrically adjusted gate structures that will result in minimal cell size while still meeting or exceeding the current electrical performance parameters.